Japanese Patent No. 3725479 (hereinafter “prior art”) discloses a synchronous memory that employs the command architecture of a volatile memory (e.g., a synchronous dynamic random access memory (SDRAM)) to access a non-volatile memory (e.g., a synchronous flash memory), where the command architecture enables decoding commands unique to the non-volatile memory.
In the synchronous memory, three command pins used as a refresh command to the SDRAM are used for a load command resistor (LCR) command to the flash memory. To perform a write operation, the synchronous memory uses the LCR command for decoding a PROGRAM setup or ERASE setup that is not used in the SDRAM but is used in the flash memory. The synchronous memory executes a LCR-ACTIVE-WRITE command cycle in which three continuous commands are issued to perform an ERASE operation to a specific memory block. In this command cycle, an ERASE set command is issued in the first cycle and the bank address of the memory block, which is being erased, is issued in the second cycle. Then, in the third cycle of the command cycle, a WRITE command is issued, and the ERASE operation starts to erase the block which has been addressed.
However, in the synchronous memory, in order to ensure compatibility with the SDRAM and to determine whether the PROGRAM setup or the ERASE setup has been instructed, the LCR command has to be issued prior to issuance of the ACTIVE command that enables an access to the synchronous memory. To this end, issuance of the LCR command becomes necessary in addition to issuance of the ACTIVE command and the WRITE command, thus increasing a chance of interrupting data output of the SDRAM by issuing the LCR command to the flash memory. Thus, the interruption of the data output of the SDRAM by the LCR command may cause difficulties in ensuring the flash memory's compatibility with the SDRAM and cause delays in memory access operations.